1. Field of the Invention
The present invention relates generally to the field of CMOS voltage references, and more particularly to a method and apparatus for performing slope and level trim in a voltage reference.
2. Description of the Related Art
Using a CMOS process to make a voltage reference has cost advantages over a precision-trimmed bipolar process. Problems with the accuracy and stability of CMOS devices must be overcome, however, in order to make a CMOS reference competitive in performance with bipolar references. Specifically, the lack of high-value stable and trimmable resistors presents a problem for circuit designers.
In order to adjust for variances in each circuit, voltage references are "trimmed" after manufacture in order to bring the output values within a specified range. This is generally accomplished by using lasers to etch away certain thin-film resistors (thereby increasing the resistance by decreasing the cross-sectional area). With proper design, most devices can be brought within the specified range using this technique. However, once the device (i.e. silicon die) is placed into a package, the mechanical stresses caused by the packaging can once again cause the circuit parameters to vary. Therefore, a competitive CMOS voltage reference must be designed such that the circuit may be "trimmed" after the final assembly of the die into a package.
One possible solution is to provide a series of resistors that can be switched in or out, as necessary, after final assembly in order to trim the slope and level of the output. This solution requires a large array of MOS switches, which have large resistance when the supply voltage is low. This resistance was found to contribute significant errors to the final reference voltage-errors that had variations with process and temperature and supply unrelated to the normal variations in the core cell. Another difficulty with using analog switches for trimming is that it is very cumbersome to change the trim range. This might be necessary, for example, in a reference with multiple voltage level options where multiple ranges of trim current are required.
Thus, it would be desirable to have an improved slope and level trim technique, suitable for use with CMOS voltage references, and providing post assembly trim.